Point-contact transistor
A germanium crystal, two gold-foil points, and the first solid-state amplifier. Vacuum tubes are still ubiquitous — nobody can yet imagine billions of these in a fingernail.
Eighty years of fab industry milestones — the inventions, the people, and the structural shifts that made the modern chip possible. Read it as the long arc that openWafer plugs into.
A germanium crystal, two gold-foil points, and the first solid-state amplifier. Vacuum tubes are still ubiquitous — nobody can yet imagine billions of these in a fingernail.
Kilby builds a phase-shift oscillator on a germanium chip; Noyce, months later, files the planar process that lets transistors share a substrate cleanly. The IC is born twice in the same year.
A field-effect transistor that finally works — silicon, oxide, metal. The structure that will define every digital chip from here on.
Pair a PMOS and an NMOS so the chip draws current only when it switches. The static power problem gets a four-decade reprieve.
An article noting that transistor counts have been doubling roughly every year. Becomes the planning constant the industry will steer by until the 2010s.
The first commercial microprocessor — 2,300 transistors on a 10 μm process. The general-purpose CPU as a product, not a one-off.
A design methodology that lets ordinary engineers (and university students) lay out their own chips. The MPW shuttle model — many small designs sharing a wafer — emerges from MOSIS, the runtime for the Mead-Conway course.
A foundry that doesn't design its own chips, just manufactures them. Decouples design from fab. Every fabless company since is downstream of this decision.
Aluminum hits its resistivity wall; IBM replaces it with copper plated into a damascene trench. Wires that finally keep up with the gates they connect.
Mechanical strain across the channel boosts mobility and keeps Moore alive past the 90 nm node. The first sign that pure scaling is over and clever physics is the new lever.
A 3D channel wrapped on three sides by the gate. Electrostatics improve enough to keep CMOS viable below 22 nm.
13.5 nm extreme-ultraviolet lithography moves from a 20-year research program into volume production. The toolchain to print 5 nm and smaller — and the geopolitical chokepoint that comes with it.
A 130 nm CMOS PDK released as open source, paired with an open-source toolchain and free MPW shuttles. The first time a commercial foundry process becomes designable by anyone with a laptop.
$280 billion to bring leading-edge fabrication back onshore. Mirrored by the EU Chips Act, Japan's Rapidus, Korea's K-Chip Belt, and India's Semicon scheme. Every major economy now treats fab capacity as strategic infrastructure.
FinFETs become nanosheet GAAs as the gate finishes wrapping the channel entirely. The last classical CMOS scaling step before exotic materials and 3D stacking take over.
Open PDKs at 130 nm and 180 nm are now production-grade. Commercial cloud IDEs ship for 22 FDX and the photonic nodes. Asia, Europe, and the US run parallel sovereign chip strategies. The barrier to designing custom silicon is now lower than it has ever been — though the barrier to manufacturing it is still high. openWafer exists to keep collapsing both.
Read the news for what's happening right now, or the platform page for how we apply this history to current design.