SoC. SoM.
Board. System.
A custom chip rarely ships alone. We design across the full ladder — from the die at the bottom to the product at the top — so each layer makes sense in the next.
A single integrated die. CPU or MCU cores, memory, peripherals, and accelerators on one piece of silicon — the smallest unit that runs your design.
Joule M5, Apple M-series, an iCE40, a sky130 chipIgnite tape-out.
JLandauer + Foundry. Design the die in the browser, route the tapeout to any open or accessible foundry.
A small carrier PCB that wraps the die in everything it needs to boot — RAM, power management, clock, debug pins, mounting interface. Designed to drop into many different host boards without redesign.
Raspberry Pi Compute Module, Coral Edge TPU SoM, the Feather-class carriers we ship.
Reference catalog. Module designs that take a die from "tape-out" to "soldered, powered, talking to the bus" without redoing the work each time.
The board the SoM (or SoC) lives on. Application-specific: connectors, sensors, antennas, displays, batteries, mechanical mounting. Where the chip stops being abstract and starts being a product.
Raspberry Pi 5, OpenBCI Cyton, an EVK dev kit, a custom medical patch PCB.
Design Services. We design the carrier when you bring a die or a SoM and need it integrated.
Mechanicals, firmware, app, retail packaging, certification, the box on the shelf. Where the silicon stops mattering as silicon and starts mattering as something a person uses.
A smart ring, a sensor patch, a satellite payload, a desktop instrument, a robot.
Design Services + partners. Full-stack engagements where the chip is one part of a larger product effort.
A design-guide philosophy.
A few principles we apply whenever we move up the ladder.
Design from math, not market.
Start from the primitive operations your application actually needs — addition, MAC, MVM, FFT, tanh, ADC, photon detection — and pick the substrate where each one is cheapest in energy and area. Markets reorganize around hardware, not the other way around.
One die, many products.
A die is expensive to spin and cheap to reuse. Design it so the same silicon can ship in an MCU module, a sensor patch, a desktop instrument, and a rack card — the carrier changes, the die doesn't.
Feather is the default carrier.
A Feather-class board is the smallest credible product unit — pocket-sized, pin-headered, harvestable-powered, distributable through Digi-Key. Every new die we design ships in a Feather first; everything else is downstream of that.
Each layer makes sense in the next.
Heat budget, power, mechanicals, certifications, connectors — they all flow upward through the ladder. A choice at the SoC layer ripples through the SoM, the Board, the System. We design every layer with the next two in mind.
No chip is a lesser chip.
A 50¢ sensor ASIC and a $5M rack accelerator share the same primitive set — the difference is surface area, parallelism, and packaging, not capability. We aim every die at every tier from the start.
Ship complete.
A SoC without a SoM, a SoM without a board, a board without firmware — each is just a milestone, not a product. We finish through the ladder, or we don't pretend we shipped.
Roadmap.
Where the platform stands today, and where each tier is heading.