2026-06-03 · Global PDK
Keysight's Advanced Design System now supports GlobalFoundries' silicon-photonics process through ADS Photonic Designer, with end-to-end electro-optical-electrical simulation in a single environment. Part of a 2026 wave of photonic-PDK consolidation that also saw Luceda announce a Luceda-PDK partnership with GF in March 2026 and SilTerra release its C-band PDK through Latitude Design Systems' PIC Studio.
2026-05-15 · EU CORPORATE
UK open-source chip-design platform ChipFlow has closed a £1.2M pre-seed (Fontinalis Partners, Fuel Ventures, InMotion Ventures, APX) and is relocating its base from Cambridge to Barcelona to access European Chips Act grants and Spanish engineering talent. ChipFlow's platform takes Amaranth (Python HDL) designs through to GDSII via the OpenROAD / LibreLane stack.
2026-04-11 · Japan FOUNDRY
Japan's Rapidus is rolling out a homegrown AI-driven design stack — Raads Generator, Raads Predictor, Raads Navigator/Indicator, Raads Manager, and Raads Optimizer — through 2026, alongside the cumulative ~¥2.35 trillion in government R&D support backing its 2nm program. Tenstorrent's Japan design center, a Rapidus partner, is also training up to 200 Japanese chip designers under a separate ¥7.5B / 5-year program.
2026-01-22 · US POLICY
DARPA's $1.4B 3D Heterogeneous Integration program — anchored at a new Texas facility — completed its tool install in Q1 2026, part of the broader $1.5B / 5-year Electronics Resurgence Initiative. The program targets defense and commercial use cases for chiplet integration and is expected to start hosting open-IP designs (POSH, IDEA, MIT-LL's Common Evaluation Platform) once the line is qualified.
2025-12-30 · China CORPORATE
Shanghai-based UniVista, founded in 2020 by ex-Synopsys and ex-Cadence engineers, filed IPO guidance on December 26. The company has raised nearly ¥4 billion (including a ¥1.7B founding round backed by the China National IC Fund Phase II) and recently launched UniVista DesignAssistant, China's first product to merge a large-scale language model with a self-developed EDA engine. It is reportedly offering free EDA trials in response to US export curbs on Synopsys and Cadence.
2025-10-14 · Korea FOUNDRY
Samsung Foundry launched SAFE Cloud, its first cloud-based one-stop design environment for fabless customers — built in partnership with Rescale and giving access to commercial EDA tools, IP, and PDK access through a browser. The platform sits alongside Samsung's CONNECT B2B portal for IP and MPW reservations, closing the loop between design and fabrication for Samsung's foundry customers.
2025-05-02 · EU POLICY
A 12-partner consortium led by imec (Belgium, with CEA, Fraunhofer, IHP, SAL, Chips-IT, CSIC, INL, TU Eindhoven, Tampere, CVUT and AGH) has been selected under the European Chips Act to build the EU Chips Design Platform — shared design infrastructure, training, and capital access for fabless startups, SMEs, and research orgs. The project runs through 2028 and is the EU's structural answer to Asia's foundry-tied design platforms.